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| EtronTech Features * Single power supply voltage of 2.3V to 3.6V * Power down features using CE1# and CE2 * Low power dissipation * Data retention supply voltage: 1.0V to 3.6V * Direct TTL compatibility for all input and output * Wide operating temperature range: -40C to 85C * Standby current @ VDD = 3.6 V IDDS2 Typical EM564081BA/BC-70/85 EM564081BA/BC-70E/85E 1 A 5 A Maximum 10 A 80 A E VDD D GND C DQ5 NC A5 A EM564081 512K x 8 Low Power SRAM Preliminary, Rev 0.7 01/2001 Pin Configuration 36-Ball BGA (CSP), Top View 1 2 3 4 5 6 A0 A1 CE2 A3 A6 A8 B DQ4 A2 WE# A4 A7 DQ0 DQ1 VDD GND F DQ6 A18 A17 DQ2 Ordering Information G DQ7 Part Number EM564081BC-70 EM564081BC-70E EM564081BA-70 EM564081BA-70E EM564081BC-85 EM564081BC-85E EM564081BA-85 EM564081BA-85E Speed 70 ns 70 ns 70 ns 70 ns 85 ns 85 ns 85 ns 85 ns IDDS2 10 A 80 A 10 A 80 A 10 A 80 A 10 A 80 A Package 6x8 BGA 6x8 BGA 8x10 BGA 8x10 BGA 6x8 BGA 6x8 BGA 8x10 BGA 8x10 BGA H A9 OE# CE1# A16 A15 DQ3 A10 A11 A12 A13 A14 Pin Description Symbol A0 - A18 DQ0 - DQ7 CE1#, CE2 OE# WE# GND VDD NC Function Address Inputs Data Inputs / Outputs Chip Enable Inputs Output Enable Read / Write Control Input Ground Power Supply No Connection Overview The EM564081 is a 4,194,304-bit SRAM organized as 512K by 8 bits. It is designed with advanced CMOS technology. This Device operates from a single 2.3V to 3.6V power supply. Advanced circuit technology provides both high speed and low power. It is automatically placed in low-power mode when chip enable (CE1#) is asserted high or (CE2) is asserted low. There are three control inputs. CE1# and CE2 are used to select the device and for data retention control, and output enable (OE#) provides fast memory access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed operating range from -40C to 85C, the EM564081 can be used in environments exhibiting extreme temperature conditions. Etron Technology, Inc. No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice. EtronTech Block Diagram EM564081 A0 MEMORY CELL ARRAY 512KX8 A18 VDD GND DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 SENSE AMP COLUMN ADDRESS DECODER W E# CE1# CE2 OE# POWER DOWN CIRCUIT Preliminary 2 Rev 0.7 January 2001 EtronTech Operating Mode Mode Read Write Output Deselect Standby X L X X CE1# CE2 L L L H H H H X OE# WE# L X H X H L H X High-Z DQ0~DQ7 DOUT DIN High-Z EM564081 Note: X = don't care. H=logic high. L=logic low. Absolute Maximum Ratings Supply voltage, VDD Input voltages, VIN Input and output voltages, VI/O Operating temperature, TOPR Storage temperature, TSTRG Soldering Temperature (10s), TSOLDER Power dissipation, PD -0.3 to +4.6V -0.3 to +4.6V -0.5 to VDD +0.5V -40 to +85C -55 to +150C 260C 0.6 W DC Recommended Operating Conditions (Ta=-40C to 85C) Symbol VDD VIH VIL Parameter Power Supply Voltage Input High Voltage Input Low Voltage Min 2.3 2.2 -0.3 (2) Typ - - - - Max 3.6 VDD + 0.3 0.6 3.6 (1) Unit V V V V VDR Data Retention Supply Voltage Note: (1) Overshoot : VDD +2.0V in case of pulse width 20ns (2) Undershoot : -2.0V in case of pulse width 20ns 1.0 Preliminary 3 Rev 0.7 January 2001 EtronTech DC Characteristics (Ta = -40C to 85C, VDD = 2.3V to 3.6V) Parameter Input low current Output low voltage Output high voltage Symbol IIL VOL VOH IIN = 0V to VDD IOL = 2.1 mA IOH = -1.0 mA VDD = 3.6 V CE1# = VIL and IDD1 Operating current CE2 = VIH and IOUT = 0mA Other Input = VIH / VIL IDD2 IDDS1 Standby current IDDS2** (Note) CE1# = VIH or CE2 = VIL CE1# = VDD - 0.2V or CE2 = 0.2V VDD = 3.6 V -70/85 VDD = 2.7 V VDD = 2.3 V VDD = 3.6 V Cycle time = 1s Cycle time = min VDD = 2.7 V VDD = 2.3 V Test Conditions Min -1 VDD 0.15 - - - - - - - - - EM564081 Typ* - - - 15 10 7 - - 1 0.8 0.5 5 Max Unit 1 0.4 - 25 15 mA 12 5 0.5 10 5 3 80 A mA A V V -70E/85E Notes: * Typical value are measured at Ta = 25C. ** In standby mode with CE1# VDD - 0.2V, these limits are assured for the condition CE2 VDD - 0.2V or CE2 0.2V. Capacitance (Ta = 25C; f = 1 MHz) Parameter Input capacitance Output capacitance Symbol CIN Min - Typ - Max 10 Unit pF Test Conditions VIN = GND COUT 10 pF VOUT = GND - - Notes: This parameter is periodically sampled and is not 100% tested. Preliminary 4 Rev 0.7 January 2001 EtronTech Read Cycle EM564081 AC Characteristics and Operating Conditions (Ta = -40C to 85C, VDD = 2.3V to 3.6V) EM564081 Symbol tRC tAA tCO1 tCO2 tOE tLZ tOLZ tHZ tOHZ tOH Write Cycle EM564081 Symbol tWC tWP tCW tAS tWR tWHZ tOW tDS tDH Write cycle time Write pulse width Chip Enable to end of write Address setup time Write Recovery time WE# Low to Output in High-Z WE# High to Output in Low-Z Data Setup Time Data Hold Time Parameter -85 - - - - - 35 - - - -70 - - - - - 30 - - - ns Unit Min Max Min Max 85 55 70 0 0 - 5 35 0 70 55 60 0 0 - 5 30 0 Read cycle time Address access time Chip Enable (CE1#) Access Time Chip Enable (CE2) Access Time Output enable access time Chip Enable Low to Output in Low-Z Output enable Low to Output in Low-Z Chip Enable High to Output in High-Z Output Enable High to Output in High-Z Output Data Hold Time Parameter -85 - 85 85 85 45 - - 35 35 - -70 - 70 70 70 35 - - 25 25 - ns Unit Min Max Min Max 85 - - - - 10 3 - - 10 70 - - - - 10 3 - - 10 AC Test Condition * Output load: 50pF + one TTL gate * Input pulse level: 0.4V, 2.4V * Timing measurements: 0.5 x VDD * tR, tF: 5ns Preliminary 5 Rev 0.7 January 2001 EtronTech Read Cycle (See Note 1) t RC EM564081 Ad d r e ss t AA t OH t CO1 CE 1 # CE2 t CO2 t HZ t OE O E# t OHZ t OLZ t LZ DO U T VALID DATA OUT Preliminary 6 Rev 0.7 January 2001 EtronTech Write Cycle1 (WE# Controlled)(See Note 4) tW C EM564081 Address t AS t WP tW R WE# t CW CE1# CE2 t CW t WHZ t OW D OUT (See Note2) (See Note3) t DS t DH D IN (See Note 5) VALID DATA IN (See Note 5) Preliminary 7 Rev 0.7 January 2001 EtronTech Write Cycle 2 (CE1# Controlled)(See Note 4) tW C EM564081 Address t AS tW P tW R W E# t CW CE1# CE2 t CW t W HZ D O UT t LZ t DS t DH D IN (See Note 5) VALID DATA IN Preliminary 8 Rev 0.7 January 2001 EtronTech Write Cycle 3 (CE2 Controlled)(See Note 4) tW C EM564081 Address t AS tW P tW R WE# t CW CE1# CE2 t CW t WHZ D OUT t LZ t DS t DH D IN (See Note 5) VALID DATA IN Note: 1. WE# remains HIGH for the read cycle. 2. If CE1# goes LOW (or CE2 goes HIGH) with or after WE# goes LOW, the outputs will remain at high impedance. 3. If CE1# goes HIGH (or CE2 goes LOW) coincident with or before WE# goes HIGH, the outputs will remain at high impedance. 4. If OE# is HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. Preliminary 9 Rev 0.7 January 2001 EtronTech Data Retention Characteristics (Ta = -40C to 85C) Symbol Data Retention Supply Voltage Data Retention Current Parameter CE1# VDD - 0.2V, CE2 0.2V, VIN VDD - 0.2V or VIN 0.2V VDD = 1.0V, CE1# VDD - 0.2V, CE2 0.2V, VIN VDD - 0.2V or VIN 0.2V Min EM564081 Typ - Max Unit VDR 1.0 3.6 V IDR tSDR tRDR - 0 tRC 0.5 - - 3.5 - - A ns ns Chip Deselect to Data Retention Mode Time Recovery Time CE1# Controlled Data Retention Mode (see Note1) V DD V DD DATA RETENTION MODE 2.7V V IH CE1 t SDR V DD - 0.2V t RDR GND CE2 Controlled Data Retention Mode (see Note2) VDD V DD DATA RE TENTI ON MOD E 2. 7V V IH CE 2 t SDR t RD R V IL 0. 2V GN D Note: 2. In CE2 controlled data retention mode, minimum standby current mode is entered when CE2 0.2V. 1. If CE1# controlled data retention mode, minimum standby current mode is entered when CE2 0.2V or CE2 VDD - 0.2V. Preliminary 10 Rev 0.7 January 2001 EtronTech Package Diagrams 36-Ball (6mm x 8mm) BGA Units in mm TOP VIEW EM564081 BOTTOM VIEW 0.10 S 0.25 S C C PIN 1 CORNER A B PIN 1 CORNER 0.30 3 4 5 6 6 5 4 3 0.05(48X) 2 1 1 2 -B0.75 -A0.20(4X) 3.75 0.15 -CSEATING PLANE Preliminary 11 Rev 0.7 January 2001 EtronTech Package Diagrams 36-Ball (8mm x 10mm) BGA Units in mm TOP VIEW EM564081 BOTTOM VIEW 0.10 S 0.25 S C C PIN 1 CORNER A B PIN 1 CORNER 0.30 3 4 5 6 6 5 4 3 0.05(48X) 2 1 1 2 -B0.75 -A0.20(4X) 3.75 0.15 -CSEATING PLANE Preliminary 12 Rev 0.7 January 2001 |
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